### Microprocessor - Fill in the Blank Questions

Fill in Blanks

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20. If a logical variable A is applied to an inverter, and the output of that inverter is applied to the input of a second inverter, the output of that second inverter is (

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**(Note: Blank is indicated by parentheses which contains the answer)**

1. To implement an n input NOR gate (by generalizing the circuit for a 2-input NOR gate shown in the textbook) we would need (

**2*n**) transistors.
2. A (

**MUX**) is used to select one of many inputs.
3. If A[15:0] = 1000110001110001, A[12:9] = (

**0110**).
4. A 2 bit by 2-bit multiplier circuit will have (

**4**) output bits.
5. It is possible to make a two input OR gate using (

**3**) two input nand gates
6. A memory, consisting of 16K entries, is 13-bit addressable. It contains (

**13*2^14**) bits of storage.
7.If 16 bits are used to specify the address space of a memory, the memory has (

**65536**) uniquely identifiable locations.
8. A decoder with n inputs can have no more than (

**2^n**) outputs.
9. If the 2 inputs of a 2 input nand gate are connected together, then the function of the nand gate is that of a/an (

**INVERTER**).
10. A (

**DECODER**) is helpful in identifying the opcode of an instruction.
11. At any time there are exactly (

**TWO**) transistors open circuited in a 2 input nand gate.
12. The function NOT { AB+CD } can be implemented using a minimum of (

**8**) transistors .
13. A circuit for adding two n bit numbers, like the one in the textbook, requires (n) full adders with (

**n+1**) bits of output.
14. A full adder generates a carry in exactly (

**4**) of the (**8**) possible combinations of its input .
15. If the delay from the inputs { A,B, Cin } to Sum is 1.5 D and to Cout is 1.0 D, then the delay of a four bit adder is (

**4.5D**)
16. When the gate is supplied with 0v the p type transistor acts as a (

**closed circuit**).
17. When the gate of a n type transistor is supplied with 0 volts, the n type transistor acts like a (

**open circuit**).
18. One can write into a gated D latch only while the (

**WE**) signal is asserted.
19. We clear an R-S latch by momentarily setting the (

**R)**signal to (**0**).**A**).
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