27 January 2012

Microprocessor - Multiple Choice Questions

Multiple Choice

#1. The minimum number of transistors required to implement a two input AND gate is

a. 2
b. 4
c. 6
d. 8
Answer: c

2. Using DeMorgan's Theorem we can convert any AND-OR structure into

Answer: a

3. For a memory with a 16-bit address space, the addressability is
a. 16 bits
b. 8 bits
c. 2^16 bits
d. Cannot be determined
Answer: d

4. Because we wish to allow each ASCII code to occupy one location in memory, most memories are _____ addressable.
c. WORD (16 bits)
d. DOUBLEWORD (32 bits)
Answer: a

5. Circuit A is a 1-bit adder; circuit B is a 1 bit multiplier.

a. Circuit A has more gates than circuit B
b. Circuit B has more gates than circuit A
c. Circuit A has the same number of gates as circuit B

(Hint: Construct the truth table for the adder and the multiplier)

Answer: a

6. When the write enable input is not asserted, the gated D latch ______ its output.
a. can not change
b. clears
c. sets
d. complements
Answer: a

7.  A structure that stores a number of bits taken "together as a unit" is a
a. gate
b. mux
c. decoder
d. register
Answer: d

8. We say that a set of gates is logically complete if we can build any circuit without using any other kind of gates.  Which of the following sets are logically complete
a. set of {AND,OR}
b. set of {EXOR, NOT}
c. set of {AND,OR,NOT}
d. None of the above
Answer: c

9. Of the following circuits, the one which involves storage is
a. RS Latch
b. mux
c. nand
d. decoder
Answer: a

10.  If the number of address bits in a memory is reduced by 2 and the
addressability is doubled, the size of the memory (i.e., the number of bits stored in the memory)
a. doubles
b. remains unchanged
c. halves
d. increases by 2^(address bits)/addressability
Answer : c

12.  If m is a power of 2, the number of select lines required for an m-input mux is:

a. m
b. 2^m
c. log2 (m)
d. 2*m
Answer: c

13.  For the number A[15:0] = 0110110010001111,  A[14:13] is ______  A[3:2].

a. less than
b. greater than
c. the same as
d . cannot be determined
Answer: c

14. Which of the following conditions is not allowed in an RS latch?

a. R is asserted, S is asserted
b. R is asserted, S is negated
c. R is negated, S is asserted
d. R is negated, S is negated
Answer: a

15. Which of the following pair of gates can form a latch?
a. a pair of cross coupled OR
b. a pair of cross copled AND
c. a pair of cross coupled NAND
d. a cross coupled NAND/OR
Answer: c


  1. Thanq very much.It is very fruitful to me.

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